1. Field
The following description relates to a processor with reconfigurable architecture, and additionally, to a method of managing configuration data of a configuration memory.
2. Description of the Related Art
Reconfigurable computing is based on the arrangement of a processor with reconfigurable hardware devices that are in an array. The behavior of such reconfigurable hardware devices, including data flow between the reconfigurable hardware devices, is tailored to perform a specific task. A reconfigurable processor may have processing performance which ranks up with dedicated hardware.
A piece of reconfigurable hardware may be referred to as a processing element (PE). The size of a PE is referred to as its granularity. A PE whose granularity is relatively large has a Coarse-Grained Reconfigurable Architecture (CGRA), whereas a PE whose granularity is relatively small has a Fine-Grained Reconfigurable Architecture (FGRA).
A Very Long Instruction Word (VLIW) machine is a CPU structure designed to use Instruction Level Parallelism (ILP). In the VLIW architecture, a processor includes multiple processing blocks. Multiple instructions that configure different steps of instructions to be sequentially executed are processed in parallel by the multiple processing blocks. Such a parallel processing architecture typically includes relatively complicated hardware to control an execution schedule of instructions.
In the VLIW architecture, an execution schedule of instructions is determined external to the processor, by a compiler which is implemented as software, and an internal execution schedule of the processor is fixed. This configuration simplifies hardware for relatively complicated control.
A reconfigurable processor includes a plurality of functional units and a configuration memory in which configuration data which determines a configuration of the functional units is stored. A configuration of the functional units may be determined by using a method in which a main processor including the functional units accesses the configuration memory to acquire configuration data and controls, for example, multiplexers to determine paths between the functional units based on the configuration data. An optimal configuration is contingent upon content of a program to be executed, and a complier determines an optimal processor configuration while compiling the program and creates configuration data based on the optimal processor configuration.
A Coarse Grained Architecture (CGA) is suitable for loop processing. Accordingly, an optimal processor configuration may be determined for each loop according to content of the loop, yielding loop-specific configuration data. If a program includes a large number of loops, a relatively large amount of configuration data is needed, which leads to the configuration memory requiring a corresponding larger capacity.